WEAVERPRO

Serial Number 98577259
688

Registration Progress

Application Filed
May 30, 2024
Under Examination
Jun 10, 2025
Approved for Publication
Apr 15, 2025
Published for Opposition
Apr 15, 2025
Registered

Attorney Assistance

NOA E-Mailed - SOU Required
Due: Dec 10, 2025 150 days

Trademark Image

WEAVERPRO

Basic Information

Serial Number
98577259
Filing Date
May 30, 2024
Published for Opposition
April 15, 2025
Drawing Code
4

Status Summary

Current Status
Active
Status Code
688
Status Date
Jun 10, 2025
Application
Pending
Classes
009

Rights Holder

Baya Systems, Inc.

03
Address
5201 Great America Parkway, Suite 100
Santa Clara, CA 95054

Ownership History

Baya Systems, Inc.

Original Applicant
03
Santa Clara, CA

Baya Systems, Inc.

Owner at Publication
03
Santa Clara, CA

Legal Representation

Attorney
Neil A. Salyards

USPTO Deadlines

Next Deadline
150 days remaining
NOA E-Mailed - SOU Required
Due Date
December 10, 2025
Extension Available
Until June 10, 2026

Application History

14 events
Date Code Type Description
Jun 10, 2025 NOAM E NOA E-MAILED - SOU REQUIRED FROM APPLICANT
Apr 15, 2025 NPUB E OFFICIAL GAZETTE PUBLICATION CONFIRMATION E-MAILED
Apr 15, 2025 PUBO A PUBLISHED FOR OPPOSITION
Apr 9, 2025 NONP E NOTIFICATION OF NOTICE OF PUBLICATION E-MAILED
Mar 18, 2025 CNSA P APPROVED FOR PUB - PRINCIPAL REGISTER
Feb 11, 2025 TROA I TEAS RESPONSE TO OFFICE ACTION RECEIVED
Feb 11, 2025 TEME I TEAS/EMAIL CORRESPONDENCE ENTERED
Feb 11, 2025 CRFA I CORRESPONDENCE RECEIVED IN LAW OFFICE
Dec 19, 2024 GNRT F NON-FINAL ACTION E-MAILED
Dec 19, 2024 CNRT R NON-FINAL ACTION WRITTEN
Dec 19, 2024 GNRN O NOTIFICATION OF NON-FINAL ACTION E-MAILED
Dec 12, 2024 DOCK D ASSIGNED TO EXAMINER
Dec 9, 2024 NWOS I NEW APPLICATION OFFICE SUPPLIED DATA ENTERED
May 30, 2024 NWAP I NEW APPLICATION ENTERED

Detailed Classifications

Class 009
Downloadable computer software used as a development tool for use in the design of integrated circuits, namely, software for interconnect design and topology optimization for design of Network on a Chip (NOC) and System on a Chip (SOC) and software for the design of coherent memory subsystems of Network on a Chip (NOC) and System on a Chip (SOC), and chiplet devices; Design libraries, namely, downloadable electronic data files for use in integrated circuit and semiconductor design, namely, data files for interconnect design and topology optimization for design of NOC, SOC devices and data files for the design of coherent memory subsystems of NOC, SOC and chiplet devices; Micronetworks for use in the design of integrated circuits, namely, micronetworks for interconnect design and topology optimization for design of NOC and SOC devices and micronetworks for the design of coherent memory subsystems of NOC, SOC and chiplet devices; integrated circuit cores in the nature of system-level protocol cores and software drivers for use in automotive electronics, consumer electronics, communication devices, and computers; Downloadable software application design tools for use in design of integrated circuits, namely, software application design tools for interconnect design and topology optimization for design of NOC and SOC devices and system-level protocol cores and device drivers for the design of coherent memory subsystems of NOC, SOC and chiplet devices

Additional Information

Pseudo Mark
WEAVER PRO

Classification

International Classes
009

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