FPGA.INFO

Serial Number 78126817
Registration 2728435
710

Registration Progress

Application Filed
May 7, 2002
Under Examination
Approved for Publication
Published for Opposition
Registered
Jun 17, 2003

Re-Apply for This Trademark

This trademark is no longer active. You may be able to file a new application for the same or similar mark.
Mark: FPGA.INFO
Previous Owner: Christopher, Charles

Trademark Image

FPGA.INFO

Basic Information

Serial Number
78126817
Registration Number
2728435
Filing Date
May 7, 2002
Registration Date
June 17, 2003
Cancellation Date
January 23, 2010
Drawing Code
1000

Status Summary

Current Status
Inactive
Status Code
710
Status Date
Jan 23, 2010

Rights Holder

Christopher, Charles

01
Address
4283 South Phillips Lane
Salt Lake City, UT 84123

Ownership History

Christopher, Charles

Original Applicant
01
Salt Lake City, UT

Christopher, Charles

Original Registrant
01
Salt Lake City, UT

Legal Representation

Attorney
Joseph A. Walkowski

USPTO Deadlines

Next Deadline
2727 days remaining
Section 8 & 9 Renewal Due (Supplemental Register) (30-Year) (Based on R.SRA event 2003-06-17)
Due Date
June 17, 2033
Grace Period Ends
December 17, 2033

Application History

13 events
Date Code Type Description Documents
Jan 23, 2010 C8.. O CANCELLED SEC. 8 (6-YR) Loading...
Apr 17, 2008 CFIT O CASE FILE IN TICRS Loading...
Jun 17, 2003 R.SR A REGISTERED-SUPPLEMENTAL REGISTER Loading...
Apr 21, 2003 CNTA O APPROVED FOR REGISTRATION SUPPLEMENTAL REGISTER Loading...
Apr 21, 2003 IUAA P USE AMENDMENT ACCEPTED Loading...
Mar 24, 2003 AUPC I AMENDMENT TO USE PROCESSING COMPLETE Loading...
Feb 27, 2003 IUAF S USE AMENDMENT FILED Loading...
Feb 27, 2003 CRFA I CORRESPONDENCE RECEIVED IN LAW OFFICE Loading...
Feb 27, 2003 TROA I TEAS RESPONSE TO OFFICE ACTION RECEIVED Loading...
Feb 27, 2003 EAAU I TEAS AMENDMENT OF USE RECEIVED Loading...
Oct 8, 2002 DOCK D ASSIGNED TO EXAMINER Loading...
Aug 27, 2002 CNRT F NON-FINAL ACTION MAILED Loading...
Aug 21, 2002 DOCK D ASSIGNED TO EXAMINER Loading...

Additional Information

Pseudo Mark
FPGA INFORMATION