FPGA DESIGNER

Serial Number 74648026
Registration 2016575
710

Registration Progress

Application Filed
Mar 17, 1995
Under Examination
Approved for Publication
Published for Opposition
Registered
Nov 12, 1996

Trademark Image

FPGA DESIGNER

Basic Information

Serial Number
74648026
Registration Number
2016575
Filing Date
March 17, 1995
Registration Date
November 12, 1996
Cancellation Date
August 16, 2003
Drawing Code
1000

Status Summary

Current Status
Inactive
Status Code
710
Status Date
Aug 16, 2003

Rights Holder

Cadence Design Systems, Inc.

03
Address
555 River Oaks Parkway
San Jose, CA 95134

Ownership History

Cadence Design Systems, Inc.

Original Applicant
03
San Jose, CA

Cadence Design Systems, Inc.

Original Registrant
03
San Jose, CA

Legal Representation

Attorney
Sally M. Abel

USPTO Deadlines

Next Deadline
472 days remaining
Section 8 & 9 (30-Year) Renewal Due (Based on registration date 1996-11-12)
Due Date
November 12, 2026
Grace Period Ends
May 12, 2027

Application History

13 events
Date Code Type Description Documents
Aug 16, 2003 C8.. O CANCELLED SEC. 8 (6-YR) Loading...
Nov 12, 1996 R.SR A REGISTERED-SUPPLEMENTAL REGISTER Loading...
Jul 10, 1996 IUAA P USE AMENDMENT ACCEPTED Loading...
Jul 10, 1996 CNTA O APPROVED FOR REGISTRATION SUPPLEMENTAL REGISTER Loading...
Jun 21, 1996 AUPC I AMENDMENT TO USE PROCESSING COMPLETE Loading...
May 31, 1996 CNFR O FINAL REFUSAL MAILED Loading...
Apr 17, 1996 CRFA I CORRESPONDENCE RECEIVED IN LAW OFFICE Loading...
Apr 17, 1996 IUAF S USE AMENDMENT FILED Loading...
Dec 7, 1995 CNRT F NON-FINAL ACTION MAILED Loading...
Oct 12, 1995 CRFA I CORRESPONDENCE RECEIVED IN LAW OFFICE Loading...
Aug 24, 1995 CNRT F NON-FINAL ACTION MAILED Loading...
Aug 16, 1995 DOCK D ASSIGNED TO EXAMINER Loading...
Aug 15, 1995 DOCK D ASSIGNED TO EXAMINER Loading...